In typical communication links the receive side circuitry detects the phase of the incoming data transitions and processes them in order to optimally sample the data. The relative phase location of the incoming data transitions are compared to a local clock (at or near the bit rate) and used to determine where edges occur, and where the data is most stable (see FIG. 1).
However, if no transitions occur for extended periods of time, phase information cannot be gathered and the risk of data drifting and a phase error accumulates between the incoming data and the local clock. If this condition persists for too long, synchronization can be lost or data errors can take place.
Data scrambling is a common technique used to increase and ensure sufficient transition density on the data to be transmitted over a communication link. Data scrambling is a logical operation which mixes the raw data to be sent with a predetermined sequence, e.g. mixture of logical ones and zeros.
This sequence may be expressed as a mathematical polynomial such as the polynomial in FIG. 2 where x represents raw data and G(x) represents scrambled data. The mixing or summing may be as simple as an Exclusive OR of the raw data and the scramble pattern.
In general, the scrambling pattern is implemented in a number of different ways depending on the designer's application and needs. A scramble pattern's complexity and length may ensure transitions on data with little or no limitations on the raw data to be transmitted.
There is always the likelihood the exact inverse of the scramble pattern is generated in the data, defeating the purpose of scrambling in the first place. In order to minimize the statistical probability of this event occurring, or if occurring, occurring for extended periods of time, more complex scramble patterns with an increased number of bits are generated.
Typically the pattern is generated using a Linear Feedback Shift Register (LFSR) where the delay through the register is equivalent to the polynomial (see FIG. 2). The summing or mixing can be as simple as a logical Exclusive OR gate, where X is the raw data, and G(x) is the scrambled pattern. Whatever operation may be performed on the transmit side, it should be complimented with the reverse operation (descramble) on the receive side.
One of the simplest and most straight forward methods to synchronize the scramble and descramble operations on the two ends of the links is through trial and error. For example, on the transmit side the scramble pattern is fixed and mixed with a known initialization sequence. The same fixed pattern is also found on the receive side, but the starting point is unknown because of the latency and initial starting point of the descramble logic. As a result, the receive side does a search to align its logic to the incoming data using an algorithm that manipulates the descramble pattern one shift register at a time. Only when the descramble pattern is perfectly matched to the incoming scrambled data will the initialization pattern be outputted on the receive side without errors.
In addition, two extreme cases exist for the purposes of power dissipation associated with scrambling data. If the raw data to be transmitted is all zeros or all ones, then the power dissipation would be relatively low without scrambling but relatively high with scrambling. If, however, there is significant switching on the raw data, then the additional power dissipation because of scrambling would be quite small or zero. The average power dissipation would be somewhere between these two extremes.
Further, different links and/or different applications require different amounts of scrambling. For example, a source synchronous link (a link where the clock is sent with the data) has much lower data transition requirements than a link where the clock must be extracted from the data and/or the local clock is at a different frequency than the incoming data. There are also system circumstances such as power savings mode where the voltage may be decreased or returned to a nominal value which creates a transient condition on the link.